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Now showing items 1-6 of 6

Realizing and functionality using single tunnel field-effect transistor

Banerjee, Saptak; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2018-07)
Investigation of timing of logic gates realized using probabilistic spin logic (PSL)

Bhatia, Ishan; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2019-07)
Improving the retention time of a dopingless 1T DRAM using gate engineering

Agarwal, Nimish; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2019-07)
An artificial neural network based incremental placer for wire length reduction

Gagandeep; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2022-08)
A practical methodology to waive marginal timing violations using machine learning

Kumar, Rajat; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2022-07)
Accounting for the correlation between low-threshold and high-threshold transistors using analytical techniques

Pandey, Prashasti; Saurabh, Sneh (Advisor) (IIIT-Delhi, 2024-06-01)

Now showing items 1-6 of 6