Abstract:
Today, in every electronic system, some information must be stored even when the system is not powered. Solid state non-volatile memories are used for storing those information which should not be lost even when the power supply is switched off. Flash memories are one of the extensively used non-volatile memories used in various portable and handheld devices ranging from wireless sensors to cellular phones. For these devices, high speed operation with low power consumption is an important aspect for efficient operation and long battery life. Here, the speed is largely limited by the time required to access the data from a particular address. Unlike memories like RAMs, flash memories require high voltages for data read, program and erase operations. However, with the evolution of VLSI technology which necessitates scaling down of supply voltages, the high speed switching from low to high voltage becomes difficult. Therefore, a high voltage management system is necessary for providing the requisite high voltages to the memory cells according to the different memory operations and also for interfacing the memory core circuits operating at high voltage level with the peripheral circuits operating at supply voltage level. In this dissertation, a wordline voltage management system has been developed in 90nm STM10 triple well CMOS technology for fast wordline charging of the memory array which mainly governs the overall access time. The overall design is also complemented with a positive/negative level shifter for high speed interfacing between the memory core circuits and the peripheral circuits. The architecture has been validated for a wide range of high voltage levels and is optimized to perform efficiently across different process corners and temperatures.
