Static timing analysis using ML models

Abstract

This project addresses the imperative role of technology libraries in digital VLSI design, focus- ing on enhancing the accuracy and adaptability of standard cell attribute modeling. Traditional libraries encounter challenges in efficiently representing complex dependencies and accommo- dating evolving design requirements. To overcome these limitations, Machine Learning (ML) models are leveraged within Static Timing Analysis (STA) tools. ML offers superior capabil- ities in capturing intricate data relationships, handling multi-dimensional dependencies, and fine-tuning for accuracy. By exploring the adoption of ML models, this project aims to ensure precise and flexible modeling of standard cell attributes, thus fostering innovation in semicon- ductor design. This report proposes integration into timing libraries using ML or DL models and regression techniques. Empirical evaluations demonstrate significant accuracy enhancements in timing analysis, paving the way for future refinement and advancements in electronic design automation. In addition to leveraging Machine Learning (ML) techniques for enhancing stan- dard cell attribute modeling in digital VLSI design, this project incorporates the construction of a TensorFlow Multilayer Perceptron (MLP) model, further augmented with Frugally Deep methodologies. Multi-Input Switching (MIS) is a critical phenomenon in digital circuits, where simultaneous transitions on multiple inputs of a logic gate can lead to increased power consumption, tim- ing variations, and reliability challenges. In this work, we present a systematic approach for analyzing MIS using OpenSTA, a static timing analysis tool. Our method involves traversing timing paths to extract all instances (gates), identifying input pins, and computing their arrival times to assess timing overlaps and potential MIS conditions. By leveraging OpenSTA’s data structures and graph traversal capabilities, we quantify timing skews and evaluate the impact of MIS on circuit performance. This approach provides a robust framework for identifying critical gates and optimizing circuit designs, ensuring timing closure and enhancing overall reliability.