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http://repository.iiitd.edu.in/xmlui/handle/123456789/196Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hemani, Rakhi | - |
| dc.contributor.author | Banerjee, Subhasis | - |
| dc.contributor.author | Guha, Apala | - |
| dc.date.accessioned | 2014-09-15T10:56:05Z | - |
| dc.date.available | 2014-09-15T10:56:05Z | - |
| dc.date.issued | 2014-09-15T10:56:05Z | - |
| dc.identifier.uri | https://repository.iiitd.edu.in/jspui/handle/123456789/196 | - |
| dc.description.abstract | Simultaneous execution of multiple threads on multicores is necessary for good resource utilization. However, such utilization calls for accurate models to predict the impact on performance due to contention of shared resources, primarily the last level cache and memory. The major challenges in developing such a model for commercial multicore machines are the unavailability of cache implementation details and the scalability of the performance prediction model for multiple threads. In this paper we propose a cache contention model addressing both these challenges. We leverage observed cache behaviour and reuse distance profile of applications for this purpose. We implement our model on a Xeon Sandy Bridge multicore and observe an RMS error of less than 0.06, for single threaded and multi-threaded workloads. Further we compare the effectiveness of using ACCORD model against the popular LRU Model and find that ACCORD is upto 2.7 times more accurate. | en_US |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | IIITD-TR-2014-004 | - |
| dc.subject | ACCORD model | en_US |
| dc.subject | LRU model | en_US |
| dc.title | ACCORD : an analytical cache contention model using reuse distances for modern multiprocessors | en_US |
| dc.type | Technical Report | en_US |
| Appears in Collections: | Year-2014 | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IIITD-TR-2014-004.pdf | 601.76 kB | Adobe PDF | View/Open |
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