IIIT-Delhi Institutional Repository

Browsing Year-2015 by Author "Deb, Sujay (Advisor)"

Browsing Year-2015 by Author "Deb, Sujay (Advisor)"

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  • Development and enhancement of verification environment for complex designs 
    Madan, Raghav; Deb, Sujay (Advisor) (2015-12-07)
    Digital VLSI design verification is a process of checking and verifying the correctness of design functionality with respect to the documented specications. Functional verification of a complex IP or sub-system, formed by ...
  • Exploration of real value modelling for complex mixed signal verification 
    Das, Pallavi; Deb, Sujay (Advisor) (2015-12-07)
    With the demand to have more functionality in today's systems, the high performance SOC will have to further accommodate Analog and Mixed Signal (AMS) designs. Also, due to increasing unpredictability and complexity of ...
  • Novel approach to reusable time-economized STIL based pattern development 
    Malhotra, Rahul; Deb, Sujay (Advisor) (2015-12-07)
    State of the art automotive microcontrollers (MCUs) implementing complex system-on-chip (SoC) architectures requires often additional functional patterns to achieve high degree of reliability. Functional pattern family ...
  • Power estimation using transaction level modeling 
    Chandoke, Nidhi; Deb, Sujay (Advisor) (2015-12-07)
    The increasing complexity of current day Systems-on-Chip and the rising market demands for low power devices has necessitated the need to perform power analysis of the complete system-on-chip at system level. This ...
  • Smart and efficient multi-scenario SoC timing closure and ECO generator 
    Sharma, Aditi; Deb, Sujay (Advisor) (2015-12-05)
    Signoff timing analysis is still considered as a critical element in the SoC design flow. With the advancements of the leading edge technologies towards the deep sub-micron realms, the performance of a multi-million ...

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