Smart and efficient multi-scenario SoC timing closure and ECO generator

Abstract

Signoff timing analysis is still considered as a critical element in the SoC design flow. With the advancements of the leading edge technologies towards the deep sub-micron realms, the performance of a multi-million transistor SoC is challenged by the aggravation of process variations. Traditionally, the performance of an integrated circuit (IC) is characterized by the clock frequency at which it operates, and is evaluated considering only worst-case gate delays. This is a pessimistic approach, which highly underestimates the performance of the design in deep sub-micron. This pessimism drives the engineers to further optimize the design, eventually increasing the design cost drastically, as analysing such a design would require consumption of more resources, adding to increase in the number of iterations. With the aggravation of process variations, the main contributor to the delay of the circuit is dominated by the interconnect delays. Hence, the number of scenarios required to analyse and x the design is enormous and ever increasing. Such a pessimism hampers with time-to-market window of product, which in worst case may be missed too. In world of large number of multi-scenarios, the engineering change order (ECO) becomes inevitable to achieve design timing closure with a low respin cost. This concern is attributed to the fact that, firstly, performing ECOs is an experimental process requiring an expert for each mode. The involvement of huge manual e ffort utilising their own respective scripts leads to signi cant amount of iterations to achieve its nal goal. Secondly, timing violations under multi-scenario design exists even after the detailed routing. In the absence of such an implementation system, that can handle xing of violations in multi-scenario design, without the involvement of manual eff ort, causes non-convergence of timing closure, making the design prone to the ping-pong e ect. This becomes a bottleneck to the design cycle time. Additionally, this approach requires large memory usage and licensed CPU resources which are already very limited. This work presents a hierarchical approach to target the xing of timing violations, gaining signi cant cycle time in overall timing closure. A complete solution for true hierarchical timing and crosstalk delay signo is presented in this work. It explores the gaps in the current approach and provides a novel solution to address them. It discusses the smart and e cient Timing Closure Methodology which first identifies the Dominant Scenarios and then prioritizes the violations for xing, in a manner which eliminates the danger of ping-pong effect, where xing one set of violations can create hundreds of new violations. This iterative approach seamlessly integrates the steps of timing closure thereby reducing 90% of the manual effort.