Sense amplier for flash memories: architectural exploration and optimal solution

Abstract

Nowadays, Non-Volatile Memories (NVM) is part of every electronic system which requires any data storage when power supply is off. Out of many available NVM solutions, Flash memories are the most powerful and cost effective solid state memory technology for portable embedded applications and mobile electronic devices. For these applications fast access time, low power and high density are critical objectives. To accomplish these, stringent design requirements are imposed upon read path of the memory. It is a well established fact that Sense Ampliers (SA) is the heart of the read path. It is upon the SA to detect and decide the content stored in memory cell. Hence, design of the sense amplifier becomes crucial because any flaw will lead to erroneous bit at the output. Key performance metrics for SA are read access time, power consumption and off set. SA must also have robustness towards any variation in temperature, supply voltage and process. Therefore, to achieve desired performance for NVM, an optimally operated SA must be utilised in the read path. In this research, we have designed and implemented frequently used industry standard sense amplifier topologies on 40nm STM40 triple well CMOS technology and elaborated upon the technical merits of these topologies. Also an e ort has been made to segment these topologies according to the speci c application areas.