Abstract:
System on Chips (SoC) targeted for high performance network applications such as Internet routers, require low latency memories combined with large storage capacities to maintain high throughputs and fast packet forwarding capabilities. To meet these demands, Dual Port SRAM (DP-SRAM) consisting of 8 transistors (T), are integrated into the SoC. However in contrast to 6T Single Port SRAMs (SP-SRAM), DP-SRAMs suffer from a limited performance, large area consumption, read-write instabilities and constraints regarding the memory capacity. In this paper an SP-SRAM based memory architecture is proposed which is able to execute two reads, one write or alternatively one read and one write within a clock cycle by combining a dedicated memory bank for XOR calculations with a Memory Association Table (MAT). In comparison to DP-SRAM the new design shows an improvement of 21%, 11% and 5% in access time, cycle time and power reduction for a 20% chance of contention respectively for a memory capable of storing 1024 words of 64 bit depth each.
