Abstract:
On chip process parameter variations have become a major challenge to meet the high density demands and the advancement in CMOS technologies. Variations in threshold voltage of transistors due to random dopant fluctuations is one of the most prominent challenges. The performance of memory sub-systems such as Static Random Access Memory (SRAM) is heavily dependent on these variations. Therefore, for sophisticated and high density electronic devices it is critical to keep a check on how tolerant they are towards these parametric fluctuations. In addition, to achieve higher yield (Y), it is desired that the SRAM bit cell qualifies in the order of less than 0.1ppb. Furthermore, the bitline differential voltage of the memory sub-system and the input-offset of the sense amplifier (SA) also deviates from their nominal values because of the parametric fluctuations. This thesis, therefore, proposes an efficient qualitative statistical analysis and Yield estimation method of SRAM sub-system which considers deviations due to variations in the process parameters of both the bit cell and the sense amplifier. The Yield of SRAM is predicted for different capacities of SRAM array by developing a model of memory sub-system in 65nm bulk CMOS technology.
The second part of this thesis tries to address some concerns related to area and power efficient designs of SRAMs and Non-Volatile Memories (NVMs). In this context, a novel, area and power proficient design of a Dual Functionality Read-Write (DFR-W) driver for SRAM sub-system has been proposed. The design is then integrated to a memory sub-system with an operating frequency of 1GHz in CMOS 65nm technology. It is compared with the conventional memory architecture keeping in perspective the power, area, leakage and speed of operation for varied memory capacities.
