Abstract:
Power consumption has become a bottleneck for modern system-on-chip (SoC) designs. With the advancement towards the deep sub-micron technology, the SoC design consists of components that prompt to a higher power density. In VLSI designs, the performance of an integrated circuit (IC) is governed by the frequency of the clock at which it operates, thus clocking is the major source of power dissipation in a design. Designing clock network is a critical task for high-performance circuits as it directly impacts clock skew, jitter, chip power and area of SoC under process variations.
Multi-bit flip-flops (MBFFs) have appeared as a low-power solution for the nanometer technology. The number of clock sinks reduces during clock tree synthesis (CTS) with the application of MBFFs. As a result, the clock network shows increment in core utilization, improvement in routing, reduction in power consumption and timing violations. The clock insertion delay (CID) is another key metric of clock network and decreasing CID results in shorter clock network, less impact on crosstalk, less impact of process variation, and reduction in hold penalties.
This work introduces a novel placement strategy in integration with the electronic design automation (EDA) tool for MBFF generation having the prerequisite knowledge of clock tree architecture. The strategy irrespective of traditional placement ow consists of MBFFs that are generated by replacing single-bit FFs iteratively during placement. FF merging and MBFF generation algorithm have been proposed. The approach is made timing aware with useful skew optimization. Experiment results show improvement in chip power by 44%, core density by 11.3% and clock power by 10.4%.
In addition to the above, another algorithm for minimizing the CID of the design has been proposed. This algorithm splits up the clock tree sinks with maximum CID to a separate pool, after the deep analysis of the clock tree structure. It also takes into account the floor plan of the chip, placement pin and the macro placement changes on the sinks. The results show that the average CID reduces by 9.2%.
