Single event effect hardened cost effective CMOS circuits

Abstract

Moving towards deep-submicron technologies, packaging density of ICs is increasing and thus the number of storage elements is also increasing on an IC. Any data corruption in these storage elements leads to huge amount of loss to companies. With decreasing technology nodes, impact of radiation is increasing. Moreover, progress in technology is witnessing more timing violations with age of the IC. This work is a study of effect of radiation induced soft errors on 180nm technology node CMOS circuits. It aims to develop radiation- hardened structures as well as explores the pre-existing designs to combat the effect of radiation on latches or Flip-Flops since Latches and Flip-Flops are critical to sequential circuits and as storage elements. Various parameters like Power dissipation, Area, and Propagation delay have been considered to evaluate the designs theoretically as well as on CAD level. According to CAD and Silicon results shared in this work, `Single Phase Clock Design' is more robust and area and power effective than state of art techniques (like DICE, TMR).