Digital LDO with analog-assisted dynamic reference correction

Abstract

Most modern circuit designs have a mix of analog and digital circuit blocks integrated on a single chip. Such designs require a dedicated power man- agement unit to provide a stable, regulated and clean power supply. This is achieved by using LDOs. Analog LDOs are accurate and have a fast transient response suitable for driving analog core on the chip. However, such LDOs are not scalable and cannot regulate lower voltage domains. Digital LDOs are thus used to supply lower voltage domains required for digital cores. Digital LDOs have a poor transient response with a poor DC load regulation. A fully on-chip 200mA class, ash ADC based digital LDO is proposed in this work with analog-assisted dynamic reference correction to improve the DC load regulation and a faster transient response. The proposed LDO can be easily scaled to drive a larger or smaller load current. An effective way to test noise at the output of the power delivery network using S-parameters has also been demonstrated in this work. Using this PDN analysis, we show a significant reduction in the simulation time. The full custom design has been implemented in STMicroelectronics 28nm FD-SOI CMOS technology and the device has been sent for fabrication. We achieve a 0.005mV/mA load regulation capability for 200mA load current variation using 5nF load capacitance, with a worst case settling time of 139ns and a peak-to-peak ripple of 7.8mV, using the post layout simulations.