Please use this identifier to cite or link to this item: http://repository.iiitd.edu.in/xmlui/handle/123456789/734
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dc.contributor.authorKapur, Shagun-
dc.contributor.authorGupta, Varshita-
dc.contributor.authorSaurabh, Sneh (Advisor)-
dc.contributor.authorGrover, Anuj (Advisor)-
dc.date.accessioned2019-10-05T07:36:36Z-
dc.date.available2019-10-05T07:36:36Z-
dc.date.issued2019-04-25-
dc.identifier.urihttp://repository.iiitd.edu.in/xmlui/handle/123456789/734-
dc.description.abstractThere are several types of electronic memory employed across the globe for a huge variety of applications. These include fast, volatile technologies such as SRAM and DRAM, and slower, non-volatile technologies such as NAND and NOR Flash. These memories, however, are limited in their scaling opportunities by their internal charge-based operation. There are multiple upcoming memories including RRAM, PCRAM, FeRAM, MRAM, etc. which attempt to combine non-volatility with speed while being non-charge based. Out of these, RRAM is a promising device that exhibits very high speeds, is highly scaleable and has low power consumption. Some issues such as variability still exist in the RRAM device, which are currently under heavy research. A vast literature exists in the domain of resistive random access memory and we have attempted to amalgamate the research by writing a review paper on the same. After reviewing the research, we have implemented multilevel RRAM operation on a novel software called SIM2RRAM.en_US
dc.language.isoen_USen_US
dc.publisherIIITD-Delhien_US
dc.subjectRRAMen_US
dc.subjectConducting filamenten_US
dc.subjectReliabilityen_US
dc.subjectMismatchesen_US
dc.subjectFOMen_US
dc.subjectMulti-biten_US
dc.titleMultilevel rram design using confinement of conducting Filamenten_US
dc.typeOtheren_US
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