Improving the retention time of a dopingless 1T DRAM using gate engineering

Abstract

In this thesis, a dopingless 1T DRAM with a high retention time is proposed. The high retention time is achieved by suppressing the diffusion current in the device which is responsible for degrading the “0” state. In the proposed device, a control gate with an appropriate workfunction is added in a region adjacent to the source. The control gate provides the necessary holes that suppress the diffusion current in the “0” state. As a result, 1/0 read current ratio also increases by 3 orders of magnitude. Furthermore, the write/hold/readbias conditions of the device and the array topology is designed suchthat the proposed DRAM cell can be integrated compactly. Additionally, it is demonstrated that the DRAM cell operates correctly under various disturb conditions.