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An energy-efficient hybrid DAC based SAR ADC using deep-submicron CMOS and large-area oxide TFT technologies

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dc.contributor.author Tiwari, Bhawna
dc.contributor.author Bahubalindruni, Pydi Ganga Mamba (Advisor)
dc.contributor.author Barquinha, Pedro (Advisor)
dc.contributor.author Goes, João (Advisor)
dc.contributor.author Deb, Sujay (Advisor)
dc.date.accessioned 2022-12-26T13:29:45Z
dc.date.available 2022-12-26T13:29:45Z
dc.date.issued 2022-12
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/1042
dc.description.abstract The successive approximation-register (SAR) analog-to-digital converters (ADCs) have excellent energy efficiency compared to other Nyquist-rate ADCs like Flash,Pipeline, etc. The simplest form of a SAR ADC employs track-and-hold (T/H) switches, a voltage comparator, a digital controller, and a capacitive digital-toanalog converter (DAC). Due to its simple architecture and highly digital and switching intensive behavior, its popularity has been boosted with technology down scaling. However, most of the designs reported in the literature employ binary-weighted capacitive DAC array, whose size increases exponentially with an increase in resolution of the ADC. This exponential increase degrades the conversion speed and energy efficiency of the SAR ADC. One of the best methods to reduce the size of the binary-weighted capacitive DAC array with the increasing resolution is to use two (or more) small-sized sub-DACs to form the complete DAC of the ADC. Though capacitive-resistive hybrid DAC-based SAR ADCs have been reported in the literature, resistive DAC tradeoff between power consumption, active area, and operating speed, which compromise the performance and energy efficiency. On the other hand, limited number of SAR ADCs with capacitive sub-DACs have been reported, which demand calibration logic and additional digital controller circuitry. Charge-Sharing (CS) and Merged-Capacitor Switching (MCS) are the two extensively employed switching schemes in the SAR ADCs. While the CS switching principle works on a single array of binary-weighted capacitive DAC, MCS works on two arrays of binary-weighted capacitive DAC for the differential implementation SAR ADC. It should be noted that though CS DAC employs a single array of capacitive DAC, it requires explicit T/H capacitors to perform the conversion algorithm. In addition, this scheme requires a pre-charging phase, in which the capacitors of the DAC array are charged to the reference voltage. As a result, for moderate to high resolution ADCs, the DAC size will be significant, and it will require a large current from the reference buffer to charge the DAC capacitors in a short duration of time. This research work presents a new hybrid capacitive DAC design for SAR ADC, which employs two switching principles, namely CS and MCS, to improve the performance metrics of the SAR ADC. The proposed hybrid DAC is purely based on capacitors, and it is designed to work without any calibration logic and additional digital controllers. Moreover, the proposed hybrid DAC architecture presents a solution where the capacitors of the MCS DAC act as T/Hcapacitors for the CS scheme when the conversion is done using this scheme, thus, eliminating the explicit T/H capacitors. On the other hand, due to the deployment of two sub-DACs in the proposed hybrid DAC design, the size of the CS sub-DAC can be reduced significantly, which helps in pre-charging the DAC capacitors in a small duration of time without drawing large current from the reference buffers. As a result, the hybrid DAC design can significantly improve the operating speed and energy efficiency of the complete ADC architecture. The proposed hybrid DAC based SAR ADC has been implemented in both deep-submicron CMOS and large-area oxide Thin-film transistor (TFT) technologies to show the design suitability for deep sub-micron and large-area semiconductor technologies. Since oxide TFT technology lacks stable and reproducible amorphous p-type transistors with reasonable performance, the complete ADC in this technology is designed using all enhancement n-type transistors with novel switches, comparator and shift register. The obtained results show FoM of the proposed SAR ADC to be 5fJ/c.s and 56nJ/c.s. in CMOS and oxide TFT technologies respectively, which are the best compared to the similar state of the art work reported in a particular technology to the best of authors knowledge. Since, the proposed CS-MCS hybrid DAC based SAR ADC design offers high energy efficiency, it finds wide applications in the field of wireless communication, biomedical, smart packaging and sensing systems. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.subject Hybrid DAC based SAR ADC en_US
dc.subject Energy efficiency en_US
dc.subject Oxide TFTs en_US
dc.subject Charge-sharing en_US
dc.subject Merged-capacitor switching en_US
dc.subject Biomedical en_US
dc.subject wireless communication en_US
dc.title An energy-efficient hybrid DAC based SAR ADC using deep-submicron CMOS and large-area oxide TFT technologies en_US
dc.type Thesis en_US

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