Hardware software co-design of 5G NR polar encoder and decoder on system-on-Chip

Abstract

Channel encoder and decoder are critical components of the wireless physical layer (PHY), enabling the transceiver to overcome transmission errors due to wireless channel fading and interference. In 5G, polar encoder and decoder are chosen for control information, while Low-Density Parity Check (LDPC) encoder and decoder are chosen for data information. Depending on the deployment platform of wireless PHY, software and hardware IP cores of these channel coders are desired. To the best of our knowledge, such IP cores are available commercially from a couple of sources only. These cores are expensive with fewer features, encrypted source codes, and hence, limited flexibility. The availability of alternate low-cost, efficient open-source IP cores is critical for indigenous 5G activities in Industry and research activities in academia. The work presented in this thesis focuses on the design and experimental validation of software and hardware IP cores for 5G polar encoder and decoder on system-on-chip (SoC). In this work, we have developed IP cores for polar encoder and decoder, rate matching and dematching, data modulator, and demodulator for downlink and uplink links. These IP cores are flexible to support various application scenarios in the 5G 3GPP specifications. The software IP cores are compatible for realization on any processor, and we have done the performance validation on dual-core ARM Cortex A9 and quad-core ARM Cortex A53 processors. The hardware IP cores are synthesizable on 7-series and Ultra-scale families of the field-programmable gate arrays (FPGA). The hardware IP cores are optimized via pipelining, memory tiling, and word length optimization. We have experimentally validated the functional correctness of the proposed IP cores for a wide range of signal-to-noise ratio (SNR), coding rates, and word lengths.