Exploring RF data converters on RFSoC platform

Abstract

The evolution of conventional field-programmable gate array (FPGA) platforms to all programmable multi-processor system-on-chip (MPSoC) platforms in the last decade has comprehensively addressed the scalability and flexibility requirements of nextgeneration electronic systems. To meet the large bandwidth and multi-standard requirements of upcoming wireless, satellite, and radar applications, the MPSoC platform with on-chip radio frequency (RF) data converters, RFSoC, has been introduced recently. Though RFSoC offers significant improvement in area, power and latency of the wireless systems over conventional multi-chip platforms, there is a significant gap in the existing literature on the configuration of the RFSoC platform for real-world demonstration. The work presented in this thesis aims to bridge this gap, thereby enabling engineers and researchers from academia and industry to efficiently and quickly configure the RFSoC platform. The first contribution of this thesis is to study various features of RF data converter in RFSoC comprising multiple analog-to-digital converters (ADC) and digitalto- analog converters (DAC) along with analog-front-end. Next, a detailed configuration process of RF data converters for any desired carrier frequency and transmission bandwidth is discussed. This includes the clock generation and configuration in RF data converters and programming of in-built interpolation and decimation stages of the DAC and ADC, respectively. The second contribution involves the real-radio performance analysis of RF data converters using an end-to-end IEEE 802.11-based wireless physical layer (PHY). Specifically, an in-depth tutorial on the integration of wireless PHY with RF data converters for any given carrier frequency and data rate is presented via various illustrative examples. The work includes the design of hardware IP cores for digital-up converters (DUC) and digital down converters (DDC) on FPGA, their integration with baseband PHY and RF data converters via hardwaresoftware co-design and PYNQ-based graphical user interface (GUI) on ARM processor for performance analysis. We validate the functional correctness of the designs in the presence of fixed-point word-length effects, quantization error due to data converters, and RF impairments via bit-error-rate (BER) performance on the RFSoC.