Abstract:
With new emerging technologies, designing with wired, wireless and optical interconnects will become easier. When designers have these three interconnect options, choosing between them and using the suitable interconnect for a particular design or part of the design will significantly impact the overall performance and cost of the system. Different applications have different requirements. No matter what kind of application or a system, with increasing number of cores, bus based communication which use shared medium do not scale. Thus Network-On-Chips become necessary to scale multicore designs. Although NoC as a concept is more than two decades old, there are still very limited real world systems in which they are deployed. NoCs are simulated using abstract behavioral models written in C/C++ to determine the behavior of NoC and to tweak their design. However it may not always be possible to translate a behavior description in C++ to a Hardware Description Language. Even if it is possible, the effort doubles up. Thus, we have developed NoxyGen which is a NoC RTL generator+ Simulator to bridge this gap. To verify the practical feasibility of the design, we burned the NoC on the FPGA and prototyped a multicore system with Microlaze soft cores connected to each other over the NoC. The Microblaze soft cores communicate with each other through Message Passing Interface(MPI) which is a standard specification for multicore communications. To extend the usability of the design to shared memory communication, we also developed a simple parameterizable cache. The future of this work would be to add directory coherence support to the cache and pass coherence messages over the network. Some parts of this report have been taken from the BTP report of the Semester 6.
