Reconfigurable and intelligent architectures for deep learning algorithms

Abstract

Throughout the course of this BTP, we e ciently implement a Deep Learning Architecture(DLWSS) for Spectrum Sensing problem on the FPGA. This involved training the model from scratch on Pytorch/Keras, extracting the weights and designing the preprocesssing and the DL model from scratch on FPGA. The developed model is benchmarked with existing iterative algorithm(OMP) for di erent types of sparsity and channels. DLWSS is optimised using Hardware Software Co- Design(HSCD) and word length optimization principles in terms of Power, Performance and Area. Finally, a basic UI is developed to visualize predictions of the model on Hardware in real time. Semester 1 was used to acquire required skillset and train the DLWSS model on a software Framework and get a basic version of Hardware implementation done. Semester 2 was used to develop the optimized implementation of DLWSS on HW along with Preprocessing Model on SW to get end to end system on the FPGA along with exploring Quantization and HSCD . Chapter 13 shows the progress made in the current semester of the BTP. The report is in continuation to the report submitted for the previous 2 semesters of the BTP.