Efficient post-silicon debug platforms for future many-core systems

Abstract

As the computation is moving towards the exascale era, more and more number of processing cores of heterogeneous natures are getting embedded in a System-on-Chip (SoC). The growing demands for high-performance and increased functionalities would further proliferate this trend in future SoCs. Such many-core systems require efficient and secured interconnection infrastructure for establishing low cost, high speed, and reliable on-chip communication. Thus, the state-of-the-art interconnect modules such as Networks-on-Chip (NoCs) are becoming extremely complex with advanced features like speculation, power management, redundancy, runtime controllability, encryption, etc. The high level of design complexity of the communication network leads to a situation where many functional bugs escape through the pre-silicon verification stage to the actual product on silicon. Even though the processing cores function correctly, bugs in interconnect can very well introduce faults like deadlock, dropped data fault, misroute, etc., which can lead to complete system failure. A substantial percentage of total system errors appear in the interconnect modules of the recent multicore architectures. This necessitates strong post-silicon debug platforms for the NoC subsystems to ensure minimal or no functional communication faults on the actual products. While post-silicon debug provides an efficient platform to remove elusive design bugs, it suffers from very poor system observability and controllability, which is limited to the I/O pins of the chip. To enhance the system’s internal observability during validation, Design for Debug (DFD) structures are instrumented to the original design that includes on-chip trace buffer, trigger unit, trace bus, etc. Traditionally, a trace based postsilicon debug platform is used that stores the runtime traces in the embedded trace buffer and later forwards them to the debug analyzer through a trace port. The drawbacks of such methods are on-chip storage cost because of the trace buffer size and slow trace transfer because of the low bandwidth trace port. In this thesis, we have focused on the development of efficient DFD structures for post-silicon validation of NoC based manycore systems, both in terms of trace reduction and high speed trace communication. Moreover, after the system validation and mass production, the DFD hardware remains vestigial on the system. Reuse of such modules for architectural purposes can compensate for the area overhead introduced by them. Therefore, we have proposed to reuse the DFD infrastructure during the in-field operation mode for the performance enhancement of the NoC based systems. To improve the efficiency of the debug infrastructure, we propose Wireless enabled NoC Debug (WiND) and Redundant Trace Elimination (RTE) frameworks. WiND performs both trace reduction and high speed trace transfer by using the augmented Wireless Interfaces (WIs) in the debug hardware for both test data and trace data communication. RTE majorly focuses on eliminating the redundant traces without degrading the internal observability of the system. To improve the reusability of the debug infrastructure, we propose Re-DeSIGN framework. In this proposal, we reuse trace buffer as extended Virtual Channels (VCs) of NoC routers for network throughput improvement, trace prioritization hardware for critical data prioritization, and trace capture modules for starvation control. This way, ReDeSIGN repurposes almost all the debug units for the performance enhancement of the system during the execution mode. On-chip router buffers consume a significant portion of the total system power. So, to minimize the buffer power in ReDeSIGN framework due to increased number of VCs, we propose DNoC, a dynamic VC power management scheme that activates only the required number of VCs based on the application need during runtime. On-chip wireless infrastructure forms the backbone for WiND and is pivotal for achieving higher debug efficiency. The wireless setup requires a Medium Access Control (MAC) mechanism for an interference free sharing of the wireless channel. The efficiency of a wireless-enabled system is majorly driven by the success of the MAC protocol, as its failure degrades the interconnect performance to a large extent. Towards this end, we propose 2DMAC and Secure MAC to improve the efficiency and security of the wireless communication respectively. 2DMAC can dynamically change the token arbitration pattern and tune the channel hold time of each WI based on its run-time traffic density and data criticality status, resulting in efficient wireless channel utilization. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer, leading to application speedup. Wireless channel being a shared medium, a corrupted WI can maliciously hold the channel, resulting in Denial of Service (DoS) or Spoofing in wireless communication. This leads to starvation of healthy WIs and under-utilization of wireless channel. Secure MAC illustrates the threat model and provides countermeasure to establish a secure MAC protocol for the wireless infrastructure embedded to the NoC based many core systems.