Abstract:
System-on-Chip (SoC) incorporates all the components of any system onto a single integrated circuit. Their compact, power-efficient architecture allows them to be used in various applications like automotive, consumer electronics, aerospace, defense, healthcare, etc. Currently, the architectures are based on separating storage and computing elements. This causes various problems known as a von-Neumann bottleneck and the power wall due to unnecessary data movement between memory and computing units. This causes a lot of power consumption and a reduction in throughput. Since almost 90% of the area is occupied by memory in a typical SoC [1], In-Memory-Computing (IMC) based architectures are being explored as an alternative to overcome the von-Neumann bottleneck problem. This, however, comes at the cost of an increased power budget for memory elements. Hence, it is of utmost importance for a designer to analyse the power consumption of any IMC-based circuit beforehand so as to design an energy-efficient architecture. An IMC architecture contains various elements like bitcells, sense amplifiers, DACs, etc. Each of these elements can have multiple different types of circuit implementations. So, to get the most energy-efficient circuit, a designer should analyze the different designs of such circuits. Existing simulators for power estimation of IMC memory arrays are highly complex and require high design efforts to change the circuit and simulate alternatives. This acts as a bottleneck in proper design space exploration. This calls for an energy estimator, enabling a designer to get a rough estimate of power consumption with reduced design efforts and faster design space exploration.
