To study the impact of process variations on NoC performance: a circuit-centric approach

Abstract

Due to technology scaling, achieving increasing bandwidth demands has become challenging and has led to the preference of Network-On-Chips (NoCs) over bus architecture as the communication infrastructure in multi-core systems-on-chips (MPSoCs). Simulation measurements of NoC performance metrics are used to estimate the expected real-time-performance of the NoC across various traffic types during the design stage. For timing-critical applications and advanced technology nodes, the granularity of simulation measurements becomes important. As per the existing literature, simulation is done using cycle-accurate system-simulators or at the register-transfer level (RTL), which takes behavioral description from the designer and uses standard cells from technology libraries to implement the design at the gate level. In this work, we implement a basic NoC design at the circuit level through different digital logic gate implementations for different parts of NoC router. This allows us to exploit various optimizations at circuit level which cannot be obtained by system-simulators or synthesis tools. Performance parameters are measured for these circuits, and Monte-Carlo simulations are done to estimate variations expected in these metrics. The delay and variation measurements are used to compare the performance as well as robustness of various implementations. Some applications may require fast operation, while some may require minimal variations in performance at the cost of speed. The approach of circuit-level analysis presented in this work is used to determine the suitability of a design for different traffic types and application requirements.