Abstract:
Achieving timing closure is a challenging task, and it becomes more complicated due to the artificial pessimism in the traditional timing models of the flip-flops. During the signoff stages, we can alleviate this problem by waiving marginal timing violations with the help of more accurate flip-flop timing models and careful analysis of the failing endpoints. In this work, we propose to develop ANN-based and SVM-based timing models for flip-flops. We demonstrate that the errors in ANN-based models and SVM-based models are less than 2% and 1%, respectively, compared to the golden SPICE results. Further, we propose a three-tiered filtering mechanism to waive marginal timing violations. It employs an ANNbased timing model to filter violations using predicted clock-to-Q delay. Then, it uses an SVM-based timing model to ensure that the marginally failing flip-flop can correctly capture the data. Finally, it checks whether surplus slack is available in the fanout of the marginally failing flip-flop that allows waiving that violation. We demonstrate the utility and robustness of the proposed methodology on TAU CONTEST’19 benchmark circuits and validated the results with SPICE simulations.
