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Realising AQM algorithms on programmable network switch hardware

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dc.contributor.author Bothra, Vedant
dc.contributor.author Peer, Aditya
dc.contributor.author Shah, Rinku (Advisor)
dc.contributor.author Maity, Mukulika (Advisor)
dc.date.accessioned 2024-03-18T13:33:44Z
dc.date.available 2024-03-18T13:33:44Z
dc.date.issued 2023-11-29
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/1386
dc.description.abstract In the world of computer networks, if we think of the internet , there is always a tradeoff between speed and how much data can be sent through the network which often leads to the use of large storage areas called buffers. This constant filling of buffers leads to network congestion which delays communication between sender and receiver. This phenomenon is called the Bufferbloat problem. The Active Queue Management (AQM) algorithms such as CoDel and PIE, are designed to control the network congestion and latency by controlling the queue delay of packets in the buffers through packet drops. Ralf et al (2018) have implemented the CoDel algorithm partially on the intel programmable tofino switch. On comparing his implementation with the standard described in RFC, Ralf’s implementation lacks the modifications which makes CoDel to do rapid transitions to drop state to solve network congestion. The existing solution based on hardware switch, partially implements the CoDel algorithm, it lacks aggressiveness in its approach and it fails when the number of flows is high and results in more spikes in latency. Moreover when dealing with high flows of data this solution tends to take more time for the avg RTT to reach below the target delay of 5ms. Currently there is no complete implementation of the CoDel algorithm available for the Intel Tofino switch. As a result our project focuses on creating a more efficient approach to decrease network congestion and enhance end to end latency by implementing the full CoDel algorithm on Intel Tofino switch. We do so by utilizing recirculated or mirrored packets between two key functions, due to constraints imposed by the Intel Tofino switch architecture. These constraints include limitations on register usage, packet access restrictions, and the need for separate registers for different functions of the CoDel algorithm. We assess the performance of the complete CoDel algorithm in comparison to the previous CoDel implementation. Our focus is on evaluating latency and throughput metrics, particularly as the number of flows increases. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.subject CoDel en_US
dc.subject Active Queue Management (AQM en_US
dc.subject Bufferbloat en_US
dc.subject P4 en_US
dc.subject ASIC en_US
dc.subject Tofino Switch en_US
dc.subject Network congestion en_US
dc.subject End-to-end latency en_US
dc.subject Programmable Network Switch en_US
dc.title Realising AQM algorithms on programmable network switch hardware en_US
dc.type Other en_US


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