Approximate computing as a means of fault tolerance in mWNoCs

Abstract

In the realm of chiplet-based computing, the advent of Network-on-Chip (NoC) technology has brought forth remarkable opportunities to harness the potential of on-chip wireless communication. This report embarks on a comprehensive journey through the dynamics of on-chip wireless channels and the challenges they pose to traditional NoC structures. One prominent issue is the detrimental effects of permanent faults within NoCs, stemming from the relentless march of technology scaling and aging defects. To address these challenges, we delve into fault-tolerant techniques, exploring mitigation through routing algorithms, hardware reconfiguration, and information redundancy. Yet, a compelling alternative emerges in the form of "Approximate Computing," which offers the unique ability to mitigate faults rather than merely correcting them. A promising technique within this domain is Bit-Shuffling (BiSu), a runtime approach that involves strategically shuffling the bits inside a flit. It effectively transfers faults to the least significant bits of each data unit, thereby mitigating the impact of multiple permanent faults. Within this landscape, our report emphasizes the significance of hybrid NoC architectures that incorporate on-chip millimeter-wave (mm-wave) wireless links in tandem with traditional wired interconnects. This novel approach strategically deploys wireless interfaces to enhance communication across widely separated cores, thereby mitigating latency and energy dissipation in large systems. These architectures adopt a hierarchical structure that utilizes subnets, central hubs, and mm-wave wireless links, propelling their advantages in terms of data rate and energy efficiency beyond the reach of traditional wireline counterparts. This exploration intertwines the small-world properties of complex networks, minimizing the average path length and opening exciting avenues for efficient communication. The results indicate that this innovative approach offers a paradigm shift in the realm of NoC design, promising greater performance, energy efficiency, and fault tolerance in chiplet-based applications. The report's findings and insights hold the potential to reshape the landscape of on-chip communication, paving the way for more reliable and efficient chiplet-based computing systems.