Design of energy e cient future CMPs with on-chip wireless interconnects

Abstract

Power density and interconnect delay have emerged as the biggest challenges for Ultra Large Scale Integration (ULSI) and System-on-Chip (SoC) designs particularly beyond 65nm gener- ation. Leakage power has been traditionally non-critical in CMOS circuits, but with extensive scaling, even it is increasing signi cantly. Dynamic Voltage/Frequency Scaling (DVFS) has been demonstrated to be one of the e ective ways to reduce the power consumption and power den- sity across the chip. Network-on-Chip (NoC) architectures improve the performance over the traditional bus based architectures. But with increasing chip sizes and long interconnects, the delay due to wired interconnects extend to multiple hops. Long range wireless links in NoC have been proven to improve the latency and energy performance tremendously. In this work, we have designed and implemented a centralized controller that applies DVFS to the processing cores. DVFS techniques reduce power consumption by scaling down voltage and frequency when possible with a little impact on performance. The proposed controller observes current state and utilization of the core and based on past state transitions, predicts the next state to set the voltage and frequency. To further reduce the power consumption, the controller also applies power gating method to the wireless interfaces used in the system. All wireless interfaces that are not in any active communication are put in idle state. The biggest advantage of centralized controller is the less overhead it adds to the system. But the delay associated with control signal transmission, particularly to remote corners of the chip is very high and so a ects the performance of controller. To reduce this delay, we propose the use of wireless interface for the same and a dual band transceiver is used for this purpose. The use of wireless interfaces de nitely reduces the delay signi cantly, but the delay values used assume ideal operating conditions. Previous works have shown that the wave propagation on chip deviates largely from ideal scenario and multiple propagation paths and wave components exist. The delay in strongest component is much more than the delay of free space direct wave. Hence the second contribution of the work is analyzing and modeling intra-chip wave propagation mechanisms. A 2D model for on-chip components is developed and using FDTD simulations, di erent propagation paths and modes are identi ed. It is observed that the free space direct wave is canceled out and re ections from interconnect layers are the dominant component of the signal. The delay in this component is almost twice the free space delay and is dependent on materials used. Finally it is shown that even with increased delay, wireless interfaces still can outperform the wired interconnects and the delay is within single cycle limits.