Fixed-point digital predistortion system for nonlinear high power amplifiers

Abstract

Radio Frequency (RF) High Power Amplifiers (HPAs) are one of the basic building blocks of modern wireless communication system. But most of these broadband wireless communication systems such as Universal Mobile Telecommunications System (UMTS) and Long Term Evolution -Advanced (LTE-Advanced) employ transmission formats such as wideband code division multiple access (WCDMA) or orthogonal frequency division multiplexing (OFDM) which have high peak-to-average power ratio (PAPR). The HPAs generally operate close to the saturation region to attain maximum efficiency, however when driven with signals having high PAPR and wide bandwidth the PA might cross over to the saturation region causing out-of-band distortions (resulting into adjacent channel interference) and in-band distortions (increase in bit error rate of the receiver). Digital Predistortion (DPD) with its high implementation flexibility has emerged as a low cost high performance alternative for the linearization of power amplifiers in the past few years. DPD includes a functional block element prior to the PA which has an inverse characteristic to that of the PA such that the overall PD-PA combination is a linear one. With the growth of wireless systems, energy usage and costs continue to increase. As a result there is an increased focus on energy efficient green radio communications. For low transmission powers, in order to achieve a noteworthy gain in power efficiency of the overall transmitter, the computational complexity of the utilized predistortion algorithms has to be kept as low as possible. Consequently, the use of fixed point arithmetic based implementation is desirable if not indispensable. In this work, we analyze the effects of fixed point implementation on DPD system. Unlike the floating point implementation, in fixed point implementation the digital predistorter and the coefficient estimation algorithm are implemented in fixed point arithmetic. We quantify the impact of this fixed point implementation on the overall performance of the digital predistorter system so that we can achieve good linearity performance with minimum number of bits for data, coefficients and arithmetic operations. The performance of the proposed fixed point digital predistorter system is evaluated in terms of adjacent channel power ratio (ACPR) and error vector magnitude (EVM) at the output of PA when a Long Term Evolution-Advanced (LTE-Advanced) signal is applied at the input.