Study, analysis and modeling of electromigration in SRAMs

Abstract

Today, the VLSI industry is matching the pace with the Moore‟s law which states that in every 18 months the number of transistors on integrated chip would get doubled. This essentially means that with the advancement of technology the size of MOSFET decreases and this in turn leads to miniaturization of wires connecting these devices. However, current flowing through these connecting wires does not decrease in appropriate proportion with the advancement in technology and as a consequence there is steep rise in the current density across integrated circuit. The increased current density may eventually result in failure of chips over a period of time due to a phenomenon called Electromigration. SRAM memories are prone to Electromigration effect considering that there is rapid advancement in its design and fabrication technology. This has the detrimental effect on the reliability of these chips. It is therefore imperative that each SRAM chips are subjected to Electromigration test in order to determine their reliability over a period of time. This additional step introduces delays in the final taping out of the chip. Conventionally, as a standard the Electromigration test is carried out in three steps using four commercially available tools. First, the capacitance of all nets along with devices is extracted. Second step estimates current in the nets followed by the generation of equivalent resistance in the nets of SRAM chips. Last step involves generation of results that provides information about the current limit and the dependence of flowing current on the associated parameters. This method is accurate but is complex and takes humungous amount of time as well as has high operating cost due to use of four tools. In this thesis work, we have developed a novel methodology which is simpler and is much faster (more than 1000 times) than the conventional technique. In addition, the proposed technique has very less operating cost. In summary, this modeling methodology requires just the Electromigration data of three memory instances i.e. one memory instance having lowest no. of bits and lowest no. of rows, second memory instance having lowest no. of bits but highest no. of rows, and third memory instance having highest no. of bits but lowest no. of columns. With this much information, the technique allows determination of the Electromigration data of any memory instance. This new technique deduces results which match favorably with those obtained from standard methodology.