Analysis and estimation of jitter sub-components

Abstract

Maintaining quality of signal transmission is a major challenge with the increasing speed of data transmission in Nano-scale VLSI technology. The decreasing voltage margins at the same time, makes it even stringent to maintain Power Integrity (PI) and Signal Integrity (SI) in high speed systems. Jitter is an important phenomenon of signal integrity. It is the difference of expected transition edges to their actual transition edges. As the data rate of serial data pattern gets higher, the bit interval time gets shorter accordingly and thus the set-up time and hold-time requirements have very less margins for designers. If the jitter exceeds beyond its specified budget, the set up time and hold time can be violated in the system. To mitigate or reduce these effects, the causes of jitter in the circuit need to be identified. That is why the decomposition of jitter into its component is useful. With the help of jitter components segregation the time required to test a link for its bit error rate can be reduced. Jitter can be classified into two major components called Deterministic Jitter (DJ) and Random Jitter (RJ). Deterministic jitter is bounded in nature while random jitter is unbounded. DJ has specific causes and is predictable while RJ is non-predictable and uncorrelated to data pattern. DJ is caused by crosstalk, Electromagnetic Interference (EMI), data pattern, etc. On the other hand, thermal noise, phase noise, process variations are the root causes of RJ. DJ can further be categorized into Periodic Jitter (PJ) and Data Dependent Jitter (DDJ). PJ is periodic, and bounded in nature. It is caused by PLL comparator, crosstalk, external noise coupling, etc., while DDJ depends on the both data being currently transmitted and the data that has been already transmitted. Inter-Symbol Interference (ISI) and Duty Cycle Distortion (DCD) are sub-components of DDJ. Reflection, discontinuities, limited bandwidth of the channel, threshold variations are the major root cause of DDJ. In this thesis, comparisons of different types of jitter estimation techniques, their strength and limitations are discussed. Further, mathematical models of different jitter sources are implemented. Finally, we introduced a new technique for ISI estimation from total jitter using clock pattern. The results of these algorithms are extensively validated with Agilent ADS.