SiGe strained FET: a computational study

Abstract

In recent years, there has been significant advancement in improving the performance of Silicon- based chips, primarily attributable to advancements in MOSFET design and manufacturing. A key manufacturing breakthrough has been the downscaling of transistors. However, as gate lengths shrink to around 10 nanometers, the necessity to enhance the mobility of charge carriers becomes apparent. SiGe, under compressive strain, emerges as a promising material offering heightened mobility while remaining compatible with existing silicon processing technologies. Nonetheless, achieving the precise combination of Si and Ge in the alloy demands a compre- hensive understanding of SiGe properties. Thus, a thorough grasp of both classical theory and the Ballistic MOSFET model is essential. This semester, our focus has centered on delving into these aspects in detail, laying a solid foundation for further exploration of SiGe in the upcoming semester. Moreover, the steady evolution of Silicon-based chips has been fueled by the relentless pur- suit of miniaturization and performance optimization. This quest has led to an exponential increase in the number of transistors packed onto integrated circuit chips, a phenomenon known as Moore’s Law. Gordon Moore’s seminal observation in 1965 laid the groundwork for un- derstanding the trajectory of transistor development, highlighting the doubling of transistor count approximately every 1.5 years. This exponential growth has been made feasible by the continuous downscaling of transistor size across successive technology generations. Nano-scale MOSFETs, characterized by their diminutive dimensions, not only offer physical advantages but also enable faster-switching operations, thereby propelling the advancement of electronic devices.