Machine learning-driven timing analysis and physical design for VLSI

Abstract

Electronic design automation (EDA) comprises software tools for designing modern integrated circuits that includes synthesis, placement, routing, timing analysis, and verification. As designs scale to billions of transistors, challenges arise from increased complexity, tighter timing margins, higher power–performance–area (PPA) demands, and long runtimes. Traditional EDA methods in VLSI design face several challenges due to their reliance on simplified analytical models and tuned heuristics. These ap- proaches often fail to capture complex, non-linear relationships among design parame- ters, resulting in limited accuracy. They are also computationally expensive and time- consuming because they depend on iterative optimization and repeated computation. As design complexity increases, traditional methods struggle to scale efficiently and require significant manual effort and expert intervention. Additionally, their ability to explore the design space is limited, often leading to suboptimal solutions, and they are less adaptable to variations and changing design conditions. Machine learning (ML) helps overcome these limitations by providing a data-driven approach that can model complex and high-dimensional relationships more efficiently. ML enables faster predic- tions compared to iterative methods, reducing computational cost and design time. It improves scalability for large and complex designs while minimizing the need for man- ual intervention. Furthermore, ML supports more efficient exploration of the design space and adapts better to variations, resulting in improved optimization and overall design quality. In the first part of this research, standard-cell modeling is made more accurate and robust by incorporating Multi-Input Switching (MIS) effects, which are ignored under the Single-Input Switching (SIS) assumption of traditional standard-cell library charac- terization. MIS can cause significant delay variations and glitches at the output, result- ing in inaccurate timing analysis, hold-time violations, signal integrity issues, increased power consumption, and incorrect sequential behavior. A novel satisfiability(SAT)- guided, ML-driven MIS characterization framework is proposed for multi-input combi- national standard cells. First, a logical analysis of the Boolean function of a given logic gate is performed to identify input patterns that can lead to MIS-induced speed-up or glitches. MIS-relevant patterns are extracted by formulating a SAT problem such that the satisfiable instances are the relevant input combinations. For each identified pattern, data is collected through SPICE simulations to capture the impact of MIS on timing attributes and glitches. This data is then used to develop an augmented technology li- brary that accurately captures MIS effects by leveraging ML techniques. Subsequently, MIS-aware STA is performed using traditional STA tool coupled with the augmented technology library. Further, to streamline the entire process of pattern extraction, data generation, and augmented library creation, an automated tool framework named LiMo (Library Model), is developed in this work. This framework integrates a SAT solver, a SPICE simulator, dataset optimization strategies, ML training/testing infrastructure, and multiprocessing capabilities to create MIS-aware augmented timing libraries. The proposed framework is validated through experimental results on ISCAS benchmark circuits. In delay calculation of multi-input combinational cells, ignoring MIS leads to Relative Root Mean Square Error (RRMSE) exceeding 40% compared to golden SPICE results, whereas LiMo-generated libraries achieve RRMSE below 7% compared to golden SPICE. For predicting the attributes of the MIS-induced glitches, employing the augmented libraries model deliver RRMSE less than 6%. Moreover, computation using augmented libraries is 10,000 × faster than the SPICE simulation. Hence, the proposed methodology can be employed in MIS-aware timing analysis for industrial designs. Building on advances in combinational standard-cell characterization, limitations of conventional timing models of sequential elements are addressed in this work. In traditional approaches, setup time (ST), hold time (HT), and clock-to-Q (C2Q) delays are modeled independently using two-dimensional lookup tables. Such a deterministic and decoupled representation fails to capture their interdependence, thereby introduc- ing pessimism that results in artificial violations and unnecessary design iterations. To address these limitations, a novel statistical, ML-driven characterization framework is proposed, in which fixed timing constraints are replaced with a probabilistic formula- tion. Instead of explicitly modeling ST and HT, an ML-based latch prediction model is proposed to estimate the probability of correct data latching under multidimensional operating conditions, including setup/hold skews and process variations. Through this approach, complex parameter dependencies are learned, and a safe operating region is defined within an extended timing space. In addition, a second ML model is developed for the prediction of C2Q delay within this extended timing region, ensuring accu- rate delay estimation even beyond conventionally defined timing constraints. Unlike traditional characterization methods, which assume fixed timing arcs, continuous and context-aware delay modeling is enabled under near-critical conditions. A hierarchi- cal violation-waiver framework is proposed to ensure that violations are safely waived. Along with latching probability, it is verified that the extension of the timing space does not introduce issues for flip-flops that were already operating safely under traditional timing constraint. The proposed framework is validated using TAU benchmark circuits in 45 nm technology and is verified against Monte Carlo SPICE simulations. Experi- mental results demonstrate 100% precision in filtering marginal violations, with no false positives, while maintaining C2Q delay prediction errors below 2% when compared to golden SPICE values within the extended timing region. In the final phase of this research, the focus shifts toward extending the application of machine learning techniques to address inaccuracies in congestion estimation dur- ing placement. Conventional early global routing (eGR) techniques, widely used for congestion-aware placement, rely on simplified models that fail to capture fine-grained variations in routing demand caused by cell dimensions, pin density, and local layout structures. This results in a mismatch with global routing (GR), leading to subopti- mal placement decisions and degraded routing closure.To address this, an ML-driven congestion prediction and alleviation framework is proposed, leveraging the ability of ML to learn complex, high-dimensional relationships between placement features and routing demand. Instead of invoking a routing engine, the model predicts congestion di- rectly from design features-including newly proposed features that capture local struc- tural and pin-access characteristics, thereby enabling fast and accurate estimation. A placement-modification method is also introduced to alleviate predicted congestion hot spots, and its effectiveness is demonstrated through loose integration with an industrial place-and-route (PnR) tool, thereby enabling more robust and congestion-aware physi- cal design flows. The proposed technique is evaluated on ISPD 2014/2015 benchmark designs and validated against golden global routing congestion obtained from a com- mercial PnR tool. An RMSE reduction of 68% in congestion prediction is achieved by the ML model compared to early global routing estimates, and an 8-30% reduction in routing congestion is enabled through improved optimization.