System-on-chip design for AI processing in edge applications

Abstract

Deep learning algorithms are pivotal in applications like image recognition, natural language processing, and autonomous systems. With their increasing deployment on edge devices such as smartphones, IoT sensors, and drones, there is a critical need for efficient hardware solutions to address the challenges of limited computational, memory, and power resources. Traditional, algorithm-specific accelerators often need more flexibility and adaptability, making them unsuit able for the diverse demands of modern DL workloads on edge devices. This report details the initial phase of designing a reconfigurable deep-learning accelerator tai lored for edge devices. By integrating state-of-the-art architectures like Eyeriss V2 for Con volutional Neural Networks (CNNs) and EdgeDRNN for Gated Recurrent Units (GRUs), the proposed solution unifies support for distinct computational patterns—parallelism in CNNs and sequential dependencies in GRUs. This unified design enhances computational efficiency and ad dresses challenges such as inflexibility, high development costs, and rapid obsolescence associated with conventional accelerators. This semester’s work focuses on analyzing the computational requirements of CNNs and GRUs and developing a top-level architectural framework. These efforts lay the groundwork for a scalable, adaptable, and environmentally sustainable accelerator capable of advancing edge AI capabilities.