Predictive analysis of safety subsystems in memories for diagnostic coverage

Abstract

Automobile safety is becoming an important subject because of the large number of electronic systems being integrated within a System on Chip (SoC) and with the use of current state-of-the-art technology, safety is becoming an even bigger challenge. ISO 26262 is a mandatory standard to ensure the safety performance in electronic systems in automobile. This standard also provides the required target of diagnostic coverage for various subsystems. For any SoC, the proper working of the memory subsystem is very critical. Faults, occurring due to aging of devices, soft errors or manufacturing defects can lead to memory operation failures. Generally, memory system failures manifest themselves as Single Bit Failures (SBFs) and Multi Bit Failures (MBFs). The Single Error Correct-Double Error Detect (SEC-DED) Error Correcting Code (ECC) is very effective for detecting SBFs, but extremely limited in detecting MBFs, owing to implementation issues. Therefore, an On-chip Safety Circuit (OSC) or Safety Circuits (SC), which is basically a hardwired mechanism, is deployed to detect these MBFs. This dissertation discusses Online Monitoring Circuits, implemented in CMOS M40 technology, in conjunction with an Error Correcting Code, to detect both Single and Multi Bit Faults. This dissertation also proposes algorithms of Predictive Analysis (PA) to provide the Diagnostic Coverage (DC) for the combination of ECC–On-chip Safety Circuit. This DC value is essentially a measure of the ability of the system to detect faults in field and can thus be a measure of the effectiveness of the safety subsystem in general. The first algorithm is used to predict DC for faults caused by manufacturing defects while the second algorithm predicts DC for in field faults.