Floorplan aware framework for optimal SRAM selection for memory subsystems

Abstract

Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a signicant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells depending on the tim- ing and the power constraints, optimal memory selection is largely a manual process. In this thesis, a framework has been proposed to optimize power, performance, and area (PPA) of a memory subsystem (MSS) by including oorplan dependent delays and power consumption in the interconnects and glue logic in the pre-RTL stage. Considering only memory PPA metrics is not su cient for optimal memory selection and leads to a suboptimal implementation. It has been observed that physical design parameters such as routing congestion and interconnect delays, have significant impact on the implementation of the MSS and including them into the framework leads to more accurate and optimal results. However, to reduce the run-time of the framework, the top N (user input) memory con gurations are pre-selected based on the PPA values of the SRAM instances and then the oorplan related metrics are estimated on the re ned results. The framework has the capability to use di erent estimates, when routing congestion is important (for example, in low cost processes with less number of metal layers). It has been shown that the interconnect delays are reduced by about 68% and dynamic power by 58%, if additional metal layers are available for routing compared to a low cost 6 metal process. Keywords: memory subsystems, oorplan aware, congestion aware, multi-objective optimization, pareto-optimal, pre-RTL estimations.