Abstract:
With reduction in size and shrinking in geometry, we have reached a point in time in which we no more can draw a direct correlation of the performance of the IC design with respect to the number of transistors on a single chip. The advancement in Electronic Design Automation and VLSI design technologies enables the circuits with increasingly higher speed to be integrated at low voltages and high densities. However this trend causes correspondingly larger voltage fluctuations in power distribution networks due to higher voltage drops such as IR-drop, L di/dt noise and LC resonance. Due to limited available silicon area and increasing clock frequencies, packaging issues and system level performance issues such as crosstalk and Electromagnetic interference are becoming increasingly significant. Rapidly switching currents due to coupling from adjacent block’s cause temporal and spatial fluctuations in the supply voltage which may cause functional failures in a design, degrading circuit performance and hence creating reliability concerns.
This dissertation addresses methodology for deciding sharing of power supplies among analog blocks (switching and non-switching blocks) taken into account the degradation of the various parameters of the s and noise due to coupling. In comparison to time domain , frequency domain characterization provides more information, simpler and are faster to perform so the analysis are done in frequency domain and results obtained are validated in time domain. Moreover a method has been proposed to predict power supply noise without actual simulation of the integrated environment by using the concept of impedance model leads to the saving of disk space and time.
