Abstract:
Embedded memories will continue to dominate the System-on-Chip (SoC) area in subsequent years. SRAMs are designed to exploit the technology limits to achieve highest storage capacity, minimum access times and operating voltages. Consequently SRAMs are prone to manufacturing losses. In advanced technology nodes, process limitations and device variations limit the SRAM performance and yield. Intra-die mismatches, process shifts, random variations in device parameters such as Threshold Voltage (Vt) and effective channel length and other defects are inevitable. The increased process spreads of modern scaled down technologies can compromise the stability of SRAM cells. All these result in the increase in probability of SRAM cells becoming weak for such highly dense memories. The performance parameters, majorly cell stability, and other Figures of Merit (FOMs) of a weak cell get deteriorated which lead to reliability issues in the SRAM. A weak cell might accidentally flip its contents during some worst case operating conditions. However, memories designed in state-of-the-art technologies like Fully Depleted Silicon on Insulator (FDSOI) possess several performance benefits due to dopant free channel, but the impact of process variations, resistive defects, transistor mismatches, IR drops and coupling still exist in SRAM core causing cell weakness. To ensure reliability of SRAMs, it is important to identify such weak cells post silicon. In this work, a comprehensive analysis on the weak cells and their effect on various FOMs have been conducted. Based on the limitations of the existing stability fault detection techniques, techniques for the identification of weak cells in SRAMs have been explored. Here, correlation based test methodologies for the efficient detection of weak bits in SRAMs have been proposed. The proposed methodology targets high speed testing at lower test costs. It enables to perform the test at nominal operating voltage and room temperature. For verification of the test methodologies, case study is conducted for a single port SRAM instance in 28nm FDSOI technology. The work presented in this thesis is carried out at ST Microelectronics.
