Abstract:
Performance of emerging multicore systems is significantly influenced by the efficiency of the communication fabric that glues the entire system together. Large number of cores results in excessive energy consumption while also increasing hop count for far apart nodes. This severely degrades network latency and throughput thereby resulting in performance bottleneck while using conventional planar metal interconnects. However, advancements in emerging network-on-chip (NoC) interconnect technology opens up possibilities to explore energy-efficient high-performance but unconventional and application-specific topologies. In this thesis, an evaluation framework for technology agnostic hybrid NoC architecture is presented. Challenges in regular NoC design space exploration are highlighted emphasizing on the increased degree of complexity in case of hybrid NoCs. Generic simulator modification guidelines are also included in view of no available standard procedure to modify existing simulators for hybrid topology. Router utilization based metric is introduced and is applied to enable design and evaluation of energy-efficient architecture by implementing dynamic voltage scaling (DVS) with power-gating. Extension to simulated annealing based floorplan engine is also proposed which not only makes the flow floorplan-aware but it also demonstrates the extensibility and agility of the framework for further development. The proposed framework is implemented on top of an existing cycle-accurate open-source network simulator. Detailed performance analysis and benchmarking undertaken in four different case studies demonstrates the cost-effectiveness and efficiency of this framework. Hybrid topologies proposed using this framework are energy-efficient and high performance.
