Abstract:
Achieving optimal floor-plans during the physical synthesis flow is an iterative and resource intensive process and its quality has a significant impact on subsequent synthesis stages in terms of runtime and quality of results. This problem intensifies due to the abundance of macros in advance technology nodes which poses challenges in the physical design flow, especially in the floor-plan stage. It has resulted in an excessive number of channels among macros that need to be spaced carefully and optimized as they consume placement and routing resources. The work presented here is two-fold: First, a tool is introduced for automatic channel space adjustment. Second, the impact of channel space minimization on the quality of results along with runtimes are investigated. Experimental results for two complex partitions of a taped out design, Design-A and Design-B, each with 3M instances including 225 and 205 macros respectively, are presented. The results indicate an existence of an optimum channel spacing in which a 35% and 124% reduction in turn-around-time is observed with same or better quality of results, when compared to the taped out version of the same.
