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High efficiency fully integrated PLL based low-dropout voltage regulator

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dc.contributor.author Singh, Ankush
dc.contributor.author Hashmi, Mohammad S. (Advisor)
dc.date.accessioned 2017-11-10T09:27:07Z
dc.date.available 2017-11-10T09:27:07Z
dc.date.issued 2017-06
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/539
dc.description.abstract Low Dropout Regulators (LDOs) are extensively used in many applications ranging from high power system to the portable application like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple which is responsible for long battery life. The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. These low dropout regulators (LDOs) typically requires output capacitors ranging from 1 µF to 10µF. The necessity of output capacitors occupies valuable board space and can add additional integrated circuit (IC) pin count. A high IC pin count can restrict LDOs for system-on-chip (SoC) solutions. Several topologies are presented in order to compose a capacitor-less LDO regulator. In this thesis a new capacitor-less LDO which has integrator based architecture with digitally controlled loop is proposed which regulates the voltage on the principle of PLL. This PLL based voltage regulator is fully integrated on-chip and is stabilized under different load conditions which gives the user an option with regard to the external capacitor. Hence, the LDO presented here is ideal for any application, whether it be for a SoC solution or stand-alone LDO. The proposed capacitor-less fully integrated LDO is designed using28nm FDSOI technology. The integrator based LDO architecture based on the phase locked loop principle provide a stable output response from 0µA to 20mA with output capacitors in the range of 0 – 1 µF. This architecture provides higher efficiency, better load and line regulation at very low input voltage than the conventional op-amp based architecture. A 1V, 20mA fully integrated on chip LDO consumes 80_A of quiescent current with a dropout voltage of 200mV. This architecture appears to be robust to the process variations and the load conditions. Experimental results confirm a load regulation of 36uV/mA. Therefore, the proposed LDO is ideal for any application with a maximum supply rail of 1.2V and requiring the load current up to 20mA. The load transients show transient glitches at the output which are less than 300 mV independent of output capacitance. Thus, the presented PLL-based LDO voltage regulator is designed for system-on-chip (SoC) solutions. en_US
dc.language.iso en_US en_US
dc.subject LDOs en_US
dc.subject High power system en_US
dc.title High efficiency fully integrated PLL based low-dropout voltage regulator en_US
dc.type Thesis en_US

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