Abstract:
The reduction in the device dimensions, the increasing switching activity and the high power consumption in the IC design cause large currents to flow in a Power Distribution network (PDN). The switching currents cause the fluctuations in the supply voltage due to high voltage drops such as IR drop and Ldi/dt drop. These fluctuations cause failures and affect the reliability of System on Chip. Therefore, a robust Power Distribution Network is essential for the effective and reliable operation of a chip.
Due to the variations in power supply, the PDN suffers from timing fluctuations, thus affecting the propagation delay of a circuit. This thesis addresses the delay variations in a CMOS inverter. The high to low and low to high propagation delays have been analyzed using mathematical models and simulations. Thus the challenge lies in reducing the delay variations due to the changes in power supply. Hence, a power delivery network needs to be modeled in order to have reduced supply variations. The capacitance between the power and ground networks known as decoupling capacitance(decap) in a PDN acts as a charge storage and helps in reduction of supply drop. Various intrinsic decaps like MIM (metal insulator metal) decaps incorporated in previous works offer limitation of large area consumption and have been ineffective in reducing the drop. Hence there is a necessity to model the passive decap effectively.
This dissertation mainly focuses on the analog and digital techniques to model the decoupling capacitance in a PDN. Firstly, the work aims at increasing the effective decap value with aid of operational amplifier and miller effect which results in the reduction of supply drop by 20%. Moreover, a sleep transistor technique has been implemented to dampen the resonance because of the addition of resistance in the circuit. Secondly, a digital technique known as charge injection method addresses the overshoot and undershoot detection and reduces the drop by 75%. The work is carried out in Cadence Virtuoso environment using 65nm technology at IIIT Delhi.
