Design of a fully on-chip linear regulator

Abstract

Power conditioning circuits form an integral part of a memory chip. Various blocks on a memory chip require uninterrupted power supply that are independent of the load conditions. The program, erase and read operations in a memory chip work at a particular supply voltage. The input / output pins start toggling immediately after the chip is turned on. Therefore, the faster startup of the regulator is also required. In this thesis, the systematic design of a two-stage linear regulator with an input supply of 3.3V ±10% and output voltage of 2.5V having ±3% accuracy on 300nm technology is stated. Quiescent current of the regulator is 20μA and full load current is 20mA. Load capacitor of the regulator varies from 50pF to 200pF and DC PSRR of the regulator is 60dB. The required startup time of the regulator is less than 1μs. Various techniques like tail current enhancement, load current enhancement, fast gate node discharge circuit, and splitting Miller capacitance have been tried to acquire the desired startup time of the regulator. The drawbacks of each methodology have been stated. Lastly, a novel capacitor splitting Miller network has been implemented to obtain startup time of less than 1μs. The tail current enhancement along with this technique provides the desired startup time. The technique has been tested across process, input supply voltage and temperature variations (PVT). The comparison between the startup time of the conventional regulator architecture and the new regulator circuit is stated as well.