Time to digital converter for all digital PLL in 65 nm CMOS technology

Abstract

A new vernier delay line time to digital converter (TDC) architecture using a tristate buffer is proposed in my thesis work. The design being implemented in this thesis work is a single stage vernier delay line time to digital converter. The single stage tristate buffer TDC has very less power consumption, no metastability issues and a very high resolution of 4 ps. This technique enables the power and resolution efficiently. Time to Digital converter has been implemented in a standard 65 nm CMOS process. Single stage time to digital converter has a resolution of 4 ps with power consumption of 72:3 μW.