Abstract:
Modern processors are capable of working at a very high frequency with the advent of
technology scaling. However, memory limits the overall speed of operation. In order
to take complete advantage of these modern high-performance processors, it is essential
to improve the data transfer rates in the memory. As per open NAND ash interface
(ONFI) standard, the current data rate is around 800MBps. Between every successive
ONFI standard, a 100% improvement in data rate has been observed. By extrapolating
the existing trend, the data rate of next generation of ONFI can be about 1600MBps.
This project aims at achieving 1333MBps to support an industrial need. Since the
speed focused on Silicon is 1333MBps, the thesis strives to achieve 1400MBps in order
to accommodate parasitics. At this high frequency, the channel response deteriorates
because of dielectric loss and Inter-Symbol Interference (ISI). Additionally, crosstalk in
parallel interface degrades the signal integrity. The technique used to restore the channel
loss is called equalization. The thesis presents a design of Continuous Time Linear
Equalization (CTLE) based gigabit receiver for ONFI parallel interface on 16nm FinFET
technology. The design consists of a CTLE, a latch, a Current Mode Logic (CML) to
Complementary MOSFET (CMOS) converter and a duty cycle corrector (DCC). A novel
design has been proposed to support rail to rail Input Common Mode Range (ICMR)
of the receiver to provide exibility to the transmitter. This receiver compensates an
estimated channel loss of 4dB at 1400MHz and provides a dc-gain of 10dB. Further, it
maintains 50_1:5% duty cycle to support Double-Data-Rate(DDR) (2.8GbBs). For a
given ICMR,a power efficiency of 1.4pJ/bit is achieved which is superior to the state-of-art designs. However, in order to support complete rail to rail ICMR the novel design
was showing 4.7pJ/bit.
