Abstract:
The crystal oscillator is widely used in the electronics industry since it has become
one of the essential parts of the reference clock for the Phase-locked loop (PLL). Highperformance systems benefit from higher frequency reference clocks. However, there is a real frequency limitation to quartz resonators. Quartz operates up to 1GHz and isnot manufactured with today’s technology. PLL has more intrinsic noise and has more power consumption. To reduce the overall noise of PLL, the reference clock must have minimum noise. Hence, this works presents the design and implementation of a low phase noise & fast startup crystal oscillator. Generally, crystal oscillators have limited current support depending on their drive level capability. The transconductance gm stage has been proposed by limiting the current which leads to improvement in phase noise. Jitter has been controlled by using the low pass filter. This circuit is capable of ensuring fast startup time with the help of its proposed crystal architecture design and transconductance design, which is presented in this work.
The proposed circuit design is implemented in TSMC 28nm CMOS technology. Two
types of power supply have been used as an external and main power supply. The
simulation results show the startup time of crystal oscillator from 120us to 150us. The
crystal oscillator’s current consumption from 362uA to 1.58mA. The phase noise of the
crystal oscillator -138dBc/Hz @1KHz. The jitter of the crystal oscillator from 1ps to
3ps. Duty Cycle of the crystal oscillator at different PVT corners is from 46% to 52%.
