IIIT-Delhi Institutional Repository

Improving the retention time of a dopingless 1T DRAM using gate engineering

Show simple item record

dc.contributor.author Agarwal, Nimish
dc.contributor.author Saurabh, Sneh (Advisor)
dc.date.accessioned 2020-06-11T07:18:00Z
dc.date.available 2020-06-11T07:18:00Z
dc.date.issued 2019-07
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/813
dc.description.abstract In this thesis, a dopingless 1T DRAM with a high retention time is proposed. The high retention time is achieved by suppressing the diffusion current in the device which is responsible for degrading the “0” state. In the proposed device, a control gate with an appropriate workfunction is added in a region adjacent to the source. The control gate provides the necessary holes that suppress the diffusion current in the “0” state. As a result, 1/0 read current ratio also increases by 3 orders of magnitude. Furthermore, the write/hold/readbias conditions of the device and the array topology is designed suchthat the proposed DRAM cell can be integrated compactly. Additionally, it is demonstrated that the DRAM cell operates correctly under various disturb conditions. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.title Improving the retention time of a dopingless 1T DRAM using gate engineering en_US
dc.type Thesis en_US

Files in this item

This item appears in the following Collection(s)

Show simple item record

Search Repository

Advanced Search


My Account