Abstract:
As technology advances,semiconductor devices are becoming less predictable. This means device failure rate increases as we move down to lower technology nodes. According to ITRS roadmap upto 80% of SOC (Silicon On Chip) area would be occupied by embedded SRAMs (eSRAM) in the next few years. These SRAM units are high density devices and is more susceptible to defects compared to other logic blocks. Along with defects, these SRAM units also suffer from reliability issues like aging impact. There are several computer applications which require extremely high level of reliability of computing system like in Automotive Industry. It is therefore becoming a growing need to detect as well as to find the impact of these defects and reliability issue on SRAM units.
In this work, we analyze the impact of these Partial resistive defects on Static
RandomAccessMemory(SRAM)addressdecoderssidewhichistheleadingcauseofsmall
delays in Wordline activation or deactivation; these are hard to detect and may result in
escapesandreliabilityproblems. HereweinvestigatetheimpactofBTIaswellasresistive
defects at a different location in address decoders. This work also contains the combined effect of both BTI and resistive errors on the decoders. This thesis work also suggests the test mode design for its detection mechanism for these defects. In this test mode, I have shown that the proposed detection mechanism should able to detect the error resistance more than 5K ohm.
