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Capacitor-less low dropout regulator (LDO)

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dc.contributor.author Gupta, Ravi Kumar
dc.contributor.author Visweswaran, G. S. (supervisor)
dc.date.accessioned 2021-04-06T04:38:01Z
dc.date.available 2021-04-06T04:38:01Z
dc.date.issued 2020-07
dc.identifier.uri http://repository.iiitd.edu.in/xmlui/handle/123456789/876
dc.description.abstract An output capacitor-less low-dropout (LDO) regulator with a wide range of load currents is proposed. It is based on the requirement of static comparator and current sinking circuit to control the gate of pmos pass gate. High gain and high UGB error amplifier is crucial in deciding the dc regulation of capless circuit. An error amplifier, current sink circuit and a high SR static comparator is sufficient for controlling the output in load transient. For 5pf output capacitance 600mV of output voltage is maintained for 0-4mA of load current. Current sink circuit works only for the time when output is low and comparator and error amplifier feedback circuit has not yet responded. After they responded to transients the current sink circuit gets turned off using the internal state of comparator. Comparator also works only for output reaches 50mV lower else error amplifier is sufficient to handle the small ripples. For dc regulation of 1% of output voltage the setup is made to respond faster. A 65nm tech with 900mV of supply is used for the design. Using gm/id technique each circuit was able to works in subthreshold region, allowing us to work on lower voltages. Pmos input subthreshold opamp of 67dB gain, 59degree PM, 1.29MHz of UGB and quiescent current of 10uA is used as error amplifier. SR of 6V/us is used for the comparison. Output voltage with settling time of 7nsec is obtained for the capless LDO. en_US
dc.language.iso en_US en_US
dc.publisher IIIT-Delhi en_US
dc.subject LDO, Linear Regulator, Pmos, Capless LDO en_US
dc.title Capacitor-less low dropout regulator (LDO) en_US
dc.type Thesis en_US


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