Abstract:
As the number of heterogeneous systems in Systems-on-Chip (SoCs) increases, bus-based interconnection architectures act as a bottleneck to meet the performance required by many applications. For systems with very high amount of parallel communication requirements buses may not provide the required bandwidth, latency, and end up consuming more power. A solution for such a communication bottleneck is the use of a switching network, called Network-on-Chip (NoC), to interconnect the modules in SoCs. NoCs design space is considerably larger when compared to a bus-based solution, as different routing and arbitration strategies can be implemented as well as different types of the communication infrastructure. Wireless Network-on-Chip (WNoC) are being explored in the academia to overcome the power and performance bottlenecks of conventional wired NoC. The WNoC has wireless hubs at specific strategic locations which optimise the communication process. This enables one-hop data transfer between far apart nodes using wireless medium in contrast to the multi-hop long-range communication in traditional NoC. These measures taken to optimise these systems make these systems vulnerable to security threats such as Denial of Service, Eavesdropping, Spoofing and Jamming Another major component of a wireless multi core system is the individual cache attached to every hub of the system. A cache is used by the CPU to decrease the average time to access data from memory. As the transistor sizes have decreased, multiple hardware and software optimization techniques have been implemented to increase the speed of accessing these memory structures. A cache partitioning technique which reduces the cache miss rates by finding an optimal solution using concepts of game theory is therefore proposed which also reduces the chances of side channel attacks simultaneously
