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Browsing by Author Saurabh, Sneh (Advisor)
Showing results 1 to 15 of 15
| Issue Date | Title | Author(s) |
| 2018-11-18 | 16 Bit retransmission based chipless RFID tag | Malhotra, Sambhav; Hashmi, Mohammad S. (Advisor); Biswas, Sanat (Advisor); Saurabh, Sneh (Advisor) |
| 2024-06-01 | Accounting for the correlation between low-threshold and high-threshold transistors using analytical techniques | Pandey, Prashasti; Saurabh, Sneh (Advisor) |
| 2025-05-19 | Analysis of circuits with partially correlated multi-Vt cell variations using sensitivity modeling and propagation | Ubaida, Mohd Abu; Saurabh, Sneh (Advisor) |
| 2022-08 | An artificial neural network based incremental placer for wire length reduction | Gagandeep; Saurabh, Sneh (Advisor) |
| 2024-04 | Implementation of neuromorphic computing framework using tunneling-based devices | Gupta, Abhinav; Saurabh, Sneh (Advisor) |
| 2019-07 | Improving the retention time of a dopingless 1T DRAM using gate engineering | Agarwal, Nimish; Saurabh, Sneh (Advisor) |
| 2025-09 | Investigating probabilistic computing: devices, circuits, and systems | Haroon, Amina; Saurabh, Sneh (Advisor) |
| 2024-12-12 | Investigation of multiple input switching impact at advanced node (7nm) | Chowdary, Nekkanti Vignesh; Saurabh, Sneh (Advisor) |
| 2019-07 | Investigation of timing of logic gates realized using probabilistic spin logic (PSL) | Bhatia, Ishan; Saurabh, Sneh (Advisor) |
| 2025-07-22 | Leveraging LLMs for automatic incremental design implementation | Shukla, Shivam; Choudhary, Utkarsh; Saurabh, Sneh (Advisor) |
| 2019-04-25 | Multilevel rram design using confinement of conducting Filament | Kapur, Shagun; Gupta, Varshita; Saurabh, Sneh (Advisor); Grover, Anuj (Advisor) |
| 2022-02 | Nanoscale tunnel field-effect transistors for digital circuit applications: design and analysis | Garg, Shelly; Saurabh, Sneh (Advisor) |
| 2022-07 | A practical methodology to waive marginal timing violations using machine learning | Kumar, Rajat; Saurabh, Sneh (Advisor) |
| 2018-07 | Realizing and functionality using single tunnel field-effect transistor | Banerjee, Saptak; Saurabh, Sneh (Advisor) |
| 2024-12-11 | Static timing analysis using ML models | Kumar, Jatin; Saurabh, Sneh (Advisor) |
