IIIT-Delhi Institutional Repository
Reducing test time using regression algorithms in post silicon validation
Login
Home
→
Electronics and Communication Engineering
→
MTech Theses
→
Year-2020
→
View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.
Reducing test time using regression algorithms in post silicon validation
Mamodia, Shivani
;
Subramanyam, A V (Advisor)
URI:
http://repository.iiitd.edu.in/xmlui/handle/123456789/1638
Date:
2020-07-01
Show full item record
Files in this item
Name:
MT18223_SHIVANI_F ...
Size:
1.044Mb
Format:
PDF
View/
Open
This item appears in the following Collection(s)
Year-2020
[13]
Search Repository
Search Repository
This Collection
Advanced Search
Browse
All of Repository
Communities & Collections
By Issue Date
Authors
Titles
Subjects
This Collection
By Issue Date
Authors
Titles
Subjects
My Account
Login
Register